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January 1997
ML4622, ML4624
Fiber Optic Data Quantizer
GENERAL DESCRIPTION
The ML4622 and ML4624 data quantizers are low noise, wideband, bipolar monolithic ICs designed specifically for signal recovery applications in fiberoptic receiver systems. They contain a wideband limiting amplifier which is capable of accepting an input signal as low as 2mVP-P with a 55dB dynamic range. This high level of sensitivity is achieved by using a DC restoration feedback loop which nulls any offset voltage produced in the limiting amplifier. The output stage is a high speed comparator circuit with both TTL and ECL outputs. An enable pin is included for added control. The Link Detect circuit provides a Link Monitor function with a user selectable reference voltage. This circuit monitors the peaks of the input signal and provides a logic level output indicating when the input falls below an acceptable level. This output can be used to disable the quantizer and/or drive an LED, providing a visible link status.
FEATURES
Data rates up to 40MHz or 80MBd Can be powered by either +5V providing TTL or raised ECL level outputs or -5.2V providing ECL levels s Low noise design: 25V RMS over bandwidth s Adjustable Link Monitor function with hystersis s Wide 55dB input dynamic range s Low power design s ML4624 is pin compatible with the ML4621
s s
APPLICATIONS
s s s
IEEE 802.3 10BASE-FL Receiver IEEE 802.5 fiber optic token ring, 4 and 16mbps Fiber Optic Data Communications and Telecommunications Receivers
ML4622/ML4624 BLOCK DIAGRAM
CF1 BIAS
CF2
ECL+
ECL-
VIN+ AMP VIN-
ECL CMP
TTL CMP
TTL OUT
CMP ENABLE
VDC VCC TTL* VCC GND VREF REF GND TTL
VTHADJ
THRESH GEN
LINK DETECT
TTL LINK MON
CTIMER *ML4624 ONLY
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ML4622, ML4624
PIN CONNECTIONS
ML4622 16-Pin DIP or SOIC (Narrow) ML4624 24-Pin Narrow DIP ML4624 28-Pin PCC
NC TTL LINK MON TTL LINK MON GND VIN- VIN+ VDC CF2 CF1 GND TTL 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CMP ENABLE VTHADJ VREF CTIMER VCC TTL OUT ECL+ ECL- CMP ENABLE VIN- VIN+ VDC CF2 CF1 NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC NC NC CTIMER VREF VTHADJ GND TTL OUT VCC TTL GND TTL ECL+ ECL- VIN- VIN+ NC VDC CF2 CF1 NC
CMP ENABLE NC 4 5 6 7 8 9 10 11 12 13 3
TTL LINK MON NC VCC NC NC 2 1 28 27 26 25 24 23 22 21 20 14 15 16 19 17 18 ECL+ ECL- GND TTL NC CTIMER VREF VTHADJ GND TTL OUT VCC TTL
TOP VIEW
NC NC NC NC
TOP VIEW
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ML4622, ML4624
PIN DESCRIPTION
NAME TTL LINK MON FUNCTION TTL Link Monitor output. Signal is low when the VIN+, VIN- inputs exceed the minimum threshold, which is set by a voltage on the VTH ADJ pin. Signal is high when the input signal level is below the threshold. Capable of driving a 10mA LED indicator. This pin can be tied to CMP ENABLE. A low voltage at this TTL input pin enables both the ECL and the TTL outputs. A high TTL voltage disables the comparator output with ECL+ high, ECL- low, and TTL OUT high. This input pin should be capacitively coupled to the input source or to filtered ground. (The input resistance is approximately 1.6k.) This input pin should be capacitively coupled to the input source or to filtered ground. (The input resistance is approximately 1.6k.) The ECL comparator negative output. Has internal pull down resistor. External pull downs are not required unless driving a large capacitive load. The ECL comparator positive output. Has internal pull down resistor. External pull downs are not required unless driving a large capacitive load. The negative supply for the TTL comparator stage. If the TTL output is not necessary, connect GND TTL to VCC. NAME VCC TTL FUNCTION The positive supply for the TTL comparator stage. If the TTL output is not necessary, connect VCC TTL to VCC . (ML4624 only) TTL data output. An external capacitor on this pin integrates an error signal which nulls the offset of the input amplifier. If the DC feedback loop is not being used, this pin should be connected to VREF. A capacitor from this pin to CF1 controls the maximum bandwidth of the amplifier. Connect to CF2 through a capacitor. Negative supply. Connect to -5.2V for ECL operation, or to ground for TTL or raised ECL operation. This input pin sets the link monitor threshold. A 2.5V reference with respect to GND. A capacitor from this pin to VCC determines the Link Monitor response time. Positive supply. Connect to ground for negative ECL operation, or to 5V for TTL or raised ECL operation.
TTL OUT VDC
CMP ENABLE
CF2
VIN-
CF1 GND
VIN+
V THADJ V REF CTIMER
ECL-
ECL+
VCC
GND TTL
3
ML4622, ML4624
ABSOLUTE MAXIMUM RATINGS
VCC - GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7.0 VCC TTL - GND TTL . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7.0 Inputs/Outputs GND . . . . . . . . . . . . . . . . . . . -0.3 to VCC +0.3 Storage Temperature Range . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering 10 sec.) . . . . . . . . . . . . . . +260C
ML4622, ML4624 ELECTRICAL CHARACTERISTICS (Note 2 and 3)
Over recommended operating conditions of TA = 0C to 70C for commercial temperature range, TA = -40C to +85C for industrial temperature range, VCC = 5V 10%, GND = 0V unless otherwise noted (Note 1).
SYMBOL ICC1 ICC2 VREF IVREF AV VIN VTHADJ Range VOS EN BW RIN IVTHADJ tPDTTL tPDECL TTL VOH TTL VOL TTL VIH TTL VIL TTL IIH TTL IIL -50 -1.6 2.0 0.8 50 0 PARAMETER VCC Supply Current (TTL Output Disabled) VCC Supply Current (TTL Output Enabled) Reference Voltage VREF Output Source Current Amplifier Gain Input Signal Range External Voltage at VTHADJ to set VTH Input Offset Input Referred Noise 3dB Bandwidth Input Resistance Input Bias Current of VTHADJ Propagation Delay Propagation Delay 2.4 0.55 1 -200 2 0.5 3 25 45 1.6 10 15 11 2.5 +200 100 1600 2.6 2.40 MIN TYP 35 55 2.50 MAX 45 70 2.60 5 UNITS mA mA V mA V/V mVP-P V mV V MHz k A ns ns V V V V A mA VIH = 2.4V VIH = 0.4V From VIN+, VIN- to TTL Out VIN = 10mVP-P From VIN+, VIN- to ECL+, ECL- VIN = 10mVP-P VCC TTL = 5V, IOH = -50A VCC TTL = 5V, IOL = 2mA VIN+, VIN- VDC = VREF (DC loop inactive) 50MHz BW CONDITIONS GND TTL = VCC GND TTL = GND
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ML4622, ML4624
ML4622, ML4624 ELECTRICAL CHARACTERISTICS (Continued)
Over recommended operating conditions of TA = 0C to 70C for commercial temperature range, TA = -40C to +85C for industrial temperature range, VCC = 5V 10%, GND = 0V unless otherwise noted.
SYMBOL VTH PARAMETER Input Threshold Voltage ML4622 ML4624 MIN 4 5 TYP 5 6 20 Common mode voltage on VIN+, VIN- Output High Voltage at ECL+, ECL- Output Low Voltage at ECL+, ECL- VCC - 1.06 VCC - 1.89 1.65 VCC - 0.7 VCC - 0.6 VCC - 1.62 VCC - 1.56 MAX 6 7 UNITS mVP-P mVP-P % V With 200 load tied to VCC - 2V With 200 load tied to VCC - 2V CONDITIONS VTHADJ = VREF (note 4) VTHADJ = VREF (note 4)
Hystersis VCM ECLVOH ECLVOL
(note 5) (note 5)
Note 1: Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with respect to ground. Note 2: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 3: Low Duty Cycle pulse testing is performed at TA. Note 4: DC Tested -- Threshold for switching TTL LINK MON from High (off) to Low (on). Note 5: Industrial temperature range specification..
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ML4622, ML4624
FUNCTIONAL DESCRIPTION
AMPLIFIER The ML4622, ML4624 have an adjustable Bandwidth limiting amplifier. Maximum sensitivity is achieved through the use of a DC restoration feedback loop and AC coupling the input. When AC coupled, the input DC bias voltage is set by an on-chip network at about 1.7V. These coupling capacitors, in conjunction with the input impedance of the amplifier, establish a high pass filter with a 3dB corner frequency, fL, at fL = 1 2 1600C (1) The above equation applies when a single capacitor is tied between CF1 and CF2. When using two capacitors of equal value (Cap1 from CF1 to VCC , Cap2 from CF2 to VCC ) the value derived for C should be doubled. Although the input is AC coupled, the offset voltage within the amplifier will be present at the amplifier's output. This is represented by VOS in figure 2. In order to reduce this error a DC feedback loop is incorporated. This negative feedback loop nulls the offset voltage, forcing VOS to be zero. Although the capacitor on VDC is nonVOUT+
VOS
VOUT-
Figure 2.
Since the amplifier has a differential input, two capacitors of equal value are required. If the signal driving the input is single ended, one of the coupling capacitors can be tied to VCC as shown in figure 1. CF1 and CF2 create a low pass filter with the corner frequency determined by the following equation fH = 1 2 800(C + 4pF) (2)
5pF +VRF CF1 BIAS 0.1 -VRF 0.01 6 FIBER OPTIC CABLE HFBR 2416 VIN- AMP ECL CMP TTL CMP TTL OUT 10 CF2 ECL+ ECL-
2 0.01 VIN+ 1 4 5 8 0.1 VDC
CMP ENABLE
3
7
-VRF VREF REF
VTHADJ
THRESH GEN
LINK DETECT
TTL LINK MON
VCC TTL* L1 4.7H +5V 0.1 + 4.7 L2 4.7H + 4.7 0.1
GND TTL
VCC
CTIMER 0.05 +VRF
GND
-VRF *ML4624 ONLY
Note:
If TTL OUT is used, tie GND TTL to unfiltered ground and remove L1. If TTL OUT and ECL outputs are both used, add 3K pulldown resistors at ECL outputs.
Figure 1. The ML4622, ML4624 Configured for 20MHz Bandwidth
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ML4622, ML4624
critical, the pole it creates can effect the stability of the feedback loop. To avoid stability problems, the value of this capacitor should be at least 10 times larger than the input coupling capacitors. COMPARATOR Two types of comparators are employed in the output section of these Quantizers. The high speed ECL comparator is used to provide the ECL level outputs and in turn drives the TTL comparator. The enable pin, CMP ENABLE, is provided to control the ECL comparator. When CMP ENABLE is low the comparators function normally. When it's high, it forces ECL+ high, ECL- low, and TTL OUT high. The CMP ENABLE pin can be controlled with TTL level signals when the Quantizer is powered by 5V and ground. LINK DETECT CIRCUIT The Link Detect circuit monitors the input signal and provides a status signal indicating when the input falls below a preset voltage level. When the input falls below the preset voltage level, the TTL Link Mon output changes from active (low) to inactive (high). This signal can be fed to the ML4662 10BASE-FL transceiver or a similar type of function to indicate a Low Light Condition. This output can also be used to disable the output data by tying it to the CMP Enable input. In many fiber optic systems, including Ethernet and Token Ring, a bit error rate is given at a minimum power level. For example, in a 10Base-FL receiver there must be less than 1 x 10-9 bit errors at a receive power level of -32.5dBm average. Designers of these systems must insure that the bit error rate is lower than the specification at the given minimum power level. One procedure to determine the sensitivity of a receiver is to start at the lowest optical power level and gradually increase the optical power until the BER is met. In this case the Link Detect circuit must not disable the receiver (i.e. CMP ENABLE should be tied to Ground). Once the sensitivity of the receiver is determined, the Link Detector circuit can be set just above the power level that meets the BER specification. This way the receiver will shut off before the BER is exceeded. The ML4622 and ML4624 quantizers have greater Link Detect sensitivity, noise immunity, and accuracy than their predecessor the ML4621. The threshold generator shifts the reference voltage at VTH ADJ through a circuit which has a temperature coefficient matching that of the limiting amplifier. The relationship between the VTH ADJ and the VTH (the peak to peak input threshold) is: VTHADJ = 417 VTH (ML4624) VTHADJ = 500 VTH (ML4622) In most cases, including 10Base-FL, 10Base-FB and Token-Ring, VTHADJ can be tied directly to VREF. However if greater sensitivity is required the circuit in figure 3 can be used to adjust the VTHADJ voltage. Even if VREF is tied to VTHADJ, it is a good idea to layout a board with these two resistors available. This will allow potential future adjustments without board revisions. The response time of the Link Detect circuit is set by the CTIMER pin. Starting from the link off state (i.e., TTL LINK MON is high), the link can be switched on if the input exceeds the set threshold for a time given by: T= C TIMER x 0.7V 700A (4) (3)
To switch the link from on to off, the above time will be doubled.
VREF R1 VTHADJ R2 (-VRF) THRESH GEN
REF
Figure 3.
BURST MODE In some fiber optic links, the idle signal is DC, or of a frequency that is substantially different from the data. For these links, a faster response time of the DC loop and the Link Monitor is required. The ML4622 and ML4624 has been designed to accommodate these two requirements. The input coupling capacitors can be relatively small and still maintain stability. With smaller input coupling capacitors and VDC capacitor a faster DC loop response time can be achieved. The Link Monitor is also enhanced to have a faster response time.
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ML4622, ML4624
ORDERING INFORMATION
PART NUMBER ML4622CP ML4622CS ML4622IS ML4624CP ML4624CQ TEMPERATURE RANGE 0C to 70C 0C to 70C -40C to 85C 0C to 70C 0C to 70C PACKAGE Molded DIP (P16) Molded SOIC (S16N) Molded SOIC (S16N) Molded DIP (P24N) Molded PCC (Q28)
(c) Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described herein may be covered by one or more of the following patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,594,376. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
DS4322_24-01
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